Emulating Dual Port Memory with Single Port Memories

摘要

The Carmel™ DSP Core, a joint development of Siemens and ICCOM, is designed for high performance signal processing applications. The Carmel is a modified Harvard architecture, with parallel processing capabilities, and a deep pipeline, which can perform up to six operations including four data memory accesses each clock cycle. The high memory bandwidth is crucial, for execution resource intensive applications, where the memory serves all the Carmel's Execution Unit components (e.g., two MACs, two ALUs, etc.) in parallel.The Carmel DSP Core is designed for the connection of a pair of dual-port memories, allowing the access of four unrelated operands each clock cycle. Dual porting optimizes memory accesses for resource intensive applications, where very high memory bandwidth and flexibility is needed. Very high memory bandwidth and flexibility, on the other hand, is not always needed. Less complex memories, that occupy smaller chip area, can provide the necessary bandwidth.Carmel's architecture provides this option. It allows the replacement of dual-port memory with twin single-port memories that save 40% of the chip area. Regions of data memoryspace can optionally be configured for single-port connection.The user of the Carmel DSP core can choose a mix of single and dual-port modules to tune up his application for optimal performance.A dual-port memory can be replaced by single-port memories on the same buses. Therefore, simultaneous access attempts to the same region of single-port memory may occur. Contentions for the single-port memory can be resolved by insertion of wait states. While the expected performance reduction is often tolerable, additional relief can be achieved by software optimization to reduce wait states (when the configuration details are incorporated).The automatic resolution of memory contentions provides portability of code. The code may be transported between applications that use different memory configurations.Carmel's development tools support mixed memory configurations. They can predict the performance of the system and provide means to adjust it.The memories can be configured to minimize the occurrence of operand collisions on the same single-port memory. The system designer, who controls the data memory structures, can organize it so that the penalties are minimized.For instance, if operand 1 addresses the dual-port region and operand2 the single-port region, then a wait will notoccur if the dual port reference is steered to a port that is not connected to the single-port memory.The easy solution for emulating dual-port within the Carmel DSP Core, provides the system designer with a flexible choice when making decisions regarding the performance - chip-area tradeoff.