High Performance VLSI Compressors for Large Data Matrix in Digital Neural Networks Implementation

摘要

A key problem for implementing high performance, high capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the imapct of carry propagation of large data matrix. In this paper, such a compresosr design based on complex complementary pass-transistor logic (C~2PL) is presneted. Some types of 3-2 compressors in C~2PL are implemented and a number of experiments are conducted to optimize their performance. Two typical building blocks, 4-2 and 7-3 compressor, are developed and their DNN applications are discussed. Compared with the complementary pass-transistor logic (CPL) and the conventional direct (CDL), our simulations show that the C~2PL compressors have the best performance in power, delay and number of transistors.