A new digital computation sequence that integrates elements of digital logic design, computer architecture, and programming is described. This four-course core sequence, introduced at Georgia Tech during the past two years, provides a system-oriented presentation instead of treating these concepts as independent topics. Key concepts include hierarchical modular design, system-level trade-offs, and computer-based design and analysis tools. Tightly coupled laboratories and computer-based assignments consolidate key concepts. Real-world design environment tools are utilized for digital logic design and simulation, instruction-level simulation, and VHDL-based architectural modeling. This restructuring of core courses is designed to better pre-pare students for the evolving design environment based on custom and semi-custom VLSI, programmable logic devices, and computer-based design tools.The first two courses provide a common core for both EE and CmpE majors. The first course introduces the design hierarchy, beginning with CMOS switches. Gate, building block, and microarchitecture levels of the hierarchy are introduced with an emphasis on abstraction and protocols between layers. The second course introduces instruction set architectures and examines implementation trade-offs. A RISC microprocessor implementation (MIPS) provides a concrete example for more abstract design tradeoffs. The third and fourth courses, taken by all CmpE and some EE majors, provide advanced material in the architecture and digital design areas including pipelining, advanced memory system design, digital logic synthesis, synchronous and asynchronous sequential system design trade-offs, and clocking schemes. These courses emphasize actual implementation trade-offs rather than relying on the idealized models typically used in lower-level courses.
展开▼
