Generation of VHDL test benches for large DSP behavioral models is complex, labor intensive task. In this paper, the authors describe a cost effective methodology for VHDL test bench generation. The authors reduce development time, and thereby cost, by using existing CASE tools to develop VHDL code. The methodology promotes reuse by providing a library of test bench elements and common DSP functions. Users are able to reuse the same basic modules many times while generating sets of test data for DSP devices within a specific application domain. In this paper, the authors report on a case study that includes two application domains: (1) radar, illustrated by a synthetic aperture radar (SAR) algorithm, and (2) 2D image processing, illustrated by a generic infra red sensing and tracking (IRST) algorithm. We demonstrate that integration of existing tools is possible by using Ilogix Express VHDL to generate VHDL code for state machine controller behavior, Cadence SPW to generate VHDL code for DSP algorithms, the Synopsis simulator system to simulate the generated VHDL code, MATLAB to provide graphical output, and a small amount of C-code to provide an intelligent user interface.
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