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Testing two-phase transition signaling based self-timed circuits in a synthesis environment

机译：在综合环境中测试基于两相过渡信令的自定时电路

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《Seventh international symposium on high-level synthesis》|1994年|P.104-111|共8页
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作者
Prabhakar Kudva; Venkatesh Akella;
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原文格式 PDF
正文语种
中图分类设计、性能分析与综合;
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2. Avoiding Hazards in Self-timed Digital Circuits Derived from Signal Transition Graphs [J] . E.C.Y. Chung, L. Kleeman Australian Telecommunication Research . 1995,第1期

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3. Using Stuck-At Tests to Form Scan-Based Tests for Transition Faults in Standard-Scan Circuits [J] . IRITH POMERANZ, SUDHAKAR M. REDDY ACM Transactions on Design Automation of Electronic Systems . 2010,第1期

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4. Testing two-phase transition signaling based self-timed circuits in a synthesis environment [C] . Kudva, P., Akella, . 1994

机译：在综合环境中测试基于两相过渡信令的自定时电路
5. Test implementation of embedded cores-based sequential circuits using Verilog HDL under Altera MAX Plus II development environment. [D] . Jin, Chuan. 2004

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机译：居民入侵者侵袭试验期间社会行为电路中细胞外信号调节激酶的激活
7. Synthesis of asynchronous circuits from signal transition graph specifications [O] . Nagalla Radhakrishna Computer Science Engineering Faculty of Engineering UNSW 1997

机译：根据信号过渡图规范合成异步电路
8. The transition of ground-based space environmental effects testing to the space environment [R] . Zaat, Stephen V., Schaefer, Glen A., Wallace, John F. 1991

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