The MIPS R6000 microprocessor relies on a new type of translation lookaside buffer --- called a
The key idea behind the TLB slice is to have both a virtual tag and a physical tag on a physically-indexed cache. Because of the virtual tag, the TLB slice needs to hold only enough physical page number bits --- typically 4 to 8 --- to complete the physical cache index, in contrast with a conventional TLB, which needs to hold both a virtual page number and a physical page number. The virtual page number is unnecessary because the TLB slice needs to provide only a hint for the translated physical address rather than a guarantee. The full physical page number is unnecessary because the cache hit logic is based on the virtual tag. Furthermore, if the cache is multi-level and references to the TLB slice are "shielded" by hits in a virtually indexed primary cache, the slice can get by with very few entries, once again lowering its cost and increasing its speed. With this mechanism, the simplicity of a physical cache can been combined with the speed of a virtual cache.
MIPS R6000微处理器依靠一种新型的转换后备缓冲器-称为 TLB切片背后的关键思想是在物理索引缓存中同时具有虚拟标签和物理标签。由于具有虚拟标签,TLB条带仅需保留足够的物理页号位(通常为4至8)即可完成物理缓存索引,而传统的TLB则需要同时保留两个虚拟页号和物理页码。虚拟页码不是必需的,因为TLB切片仅需要为转换后的物理地址提供提示,而不是保证。不需要完整的物理页号,因为高速缓存命中逻辑基于虚拟标记。此外,如果高速缓存是多级的,并且通过虚拟索引的主高速缓存中的命中来“屏蔽”对TLB条带的引用,则条带可以通过很少的条目获得访问,从而再次降低了其成本并提高了其速度。通过这种机制,可以将物理缓存的简单性与虚拟缓存的速度结合在一起。 P>
机译:现代微处理器的地址转换机制的敏捷后硅验证方法
机译:测试数据的生成,以验证微处理器中的缓存机制和地址转换
机译:利用网络地址转换的网络安全机制
机译:TLB slice-一种低成本的高速地址转换机制
机译:利用地址空间的连续性来加快TLB未命中处理。
机译:一种高速低成本VLSI系统能够用于动态视觉传感器数据分类的片上在线学习
机译:测试高速工具进行网络地址转换