Scalable shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. In addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory and the fast processors. Unless carefully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. The set of allowable memory access orderings forms the memory consistency model or event ordering model for an architecture.
This paper introduces a new model of memory consistency, called
本文介绍了一种新的内存一致性模型,称为“
机译:通过模型检查来验证共享内存多处理器上的顺序一致性
机译:大规模共享内存多处理器的可伸缩屏障同步
机译:基于队列的自适应锁定算法,用于共享内存多处理器上的可伸缩资源分配
机译:可伸缩共享内存多处理器中的内存一致性和事件排序
机译:具有一致的高速缓存的大型共享内存多处理器中TLB一致性解决方案的性能评估。
机译:成人的最早记忆报告:事件年龄和叙事特征的一致性
机译:共享内存多处理器的内存一致性模型的性能评估
机译:减轻大规模共享内存多处理器矩阵计算中的内存争用。