Cache consistency in a shared-memory multiprocessor system

摘要

The method involves processing, by a processor, a request to write data to an address of a cache memory (22) of the processor, and transmitting the address to other processors. The former processor receives an indicator indicating whether the former processor must perform a memory operation on the address. The data in the memory are maintained at modified state if a marker associated to the data is in a state, otherwise, the former processor transmits a request to write the data in a shared memory and marks the data to invalid state, when the indicator indicates to perform memory operation. Independent claims are also included for the following: (1) a digital processor (2) a system comprising several processors.