A small-sized (less than 2mm2 total analog and radio area) sub-GHz radio SoC for low power and low data-rate wireless applications is presented. The SoC has been equipped with a low-power analog-to-digital conversion scheme having a variable over-sampling ratio, multi-sampling-rate channel select filtering, and inductor-less RF front-end circuits incorporating a high output power stair-like shaping CMOS power-amplifier with a duty-imbalance-compensated level-shifter. The SoC, fabricated with 90nm CMOS, occupies only 3.5mm2. It has a sensitivity of −118dBm in a 2.4kbps FSK mode for a 433MHz band, and channel selectivity for data rates ranging from 1.0 to 240kbps.
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