首页> 外文会议>Symposium on VLSI Circuits >A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond

【24h】

A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond

机译：分布式全球可更换冗余冗余方案，用于子半微米ULSI存储器及以后

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

A Distributed Globally Replaceable Redundancy (DGR) scheme has been developed, which realizes a higher optimization of trade-off between yield and chip size. A newly developed yield simulator has demonstrated the effectiveness of the DGR scheme.

机译：开发了分布式全球可更换冗余（DGR）方案，这实现了屈服和芯片尺寸之间的折衷优化。新开发的产量模拟器已经证明了DGR方案的有效性。

著录项

来源
《Symposium on VLSI Circuits》|1993年||共2页
会议地点
作者
Sato H.; Yamagata T.; Fujita K.; Nisimura Y.; Anami K.;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类自动化技术、计算机技术;
关键词
redundancy; MOS integrated circuits; SRAM chips; DRAM chips; VLSI; distributed globally replaceable redundancy scheme; sub-half micron ULSI memories; yield simulator; static RAM; dynamic RAM; 0.5 micron;

机译：冗余;MOS集成电路;SRAM芯片;DRAM芯片;VLSI;分布式全球可更换冗余方案;次半微米ULSI存储器;产量模拟器;静态RAM;动态RAM;0.5微米;0.5微米;0.5微米;0.5微米;

相似文献

外文文献
中文文献
专利

1. A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond [J] . Yamagata T., Sato H. IEEE Journal of Solid-State Circuits . 1996,第2期

机译：适用于半微米以下ULSI存储器的分布式全局可替换冗余方案
2. A Built-in Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy [J] . Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2008,第1a3期

机译：具有两级冗余的随机访问存储器的内置冗余分析方案
3. A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy [J] . Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang Journal of Electronic Testing . 2008,第1a3期

机译：具有两级冗余的随机访问存储器的内置冗余分析方案
4. A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond [C] . Sato, H., Yamagata, . 1993

机译：适用于半微米以下ULSI存储器的分布式全局可替换冗余方案
5. Ternary content addressable memory directed redundancy for semiconductor memory yield enhancement [D] . Joly, Craig. 2004

机译：半导体内存屈服增强的三元内容可寻址内存定向冗余
6. Mittag-Leffler synchronization of delayed fractional-order bidirectional associative memory neural networks with discontinuous activations: state feedback control and impulsive control schemes [O] . Xiaoshuai Ding, Jinde Cao, Xuan Zhao, -1

机译：具有不连续激活的延迟分数阶双向联想记忆神经网络的Mittag-Leffler同步：状态反馈控制和脉冲控制方案
7. Distributed Edge Caching Scheme Considering the Tradeoff Between the Diversity and Redundancy of Cached Content [O] . Wang, Shuo, Zhang, Xing, Yang, Kun, 2017

机译：考虑到数据流之间权衡的分布式边缘缓存方案缓存内容的多样性和冗余
8. Global arrays: A portable (open quotes)shared-memory(close quotes) programming model for distributed memory computers [R] . Harrison, R. J. , Nieplocha, J. , Littlefield, R. J. 1994

机译：全局数组：分布式内存计算机的可移植（开放引号）共享内存（close quotes）编程模型

A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond

摘要

著录项

相似文献

相关主题

期刊订阅