A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET

摘要

This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12 data slicers and 2 error slicers. The quad-rate voltage-mode transmitter implements delay based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband LC PLL is distributed to eight transceiver channels. In each channel, an ILO generates eight-phase clocks that feed an 8-bit CMOS PI. The transceiver achieves <1e-12 BER over 30mm channel @106.25Gb/s and over 20mm channel @112Gb/s.