Automatic layout algorithms, placement and routing, for function blocks of CMOS gate arrays are presented.
The placement algorithm assigns transistors to basic cells so as to minimize the number of cells used and to minimize the number of interconnections crossing cut-lines. The former objective is achieved by finding a maximum matching and the latter is achieved by iterative interchanges of transistor pairs. A new routing technique based on channel routing methods is introduced to handle the internal cell area. It intends to route with the primary use of the first layer and with the least use of tracks.
A program based on the algorithms has been developed and applied to many block designs for up to 200 transistors. The results show that the presented algorithms could realize as good a layout as manual.
介绍了CMOS门阵列功能块的自动布局算法,布局和布线。 P>
放置算法将晶体管分配给基本单元,以使使用的单元数最少,并使与切割线交叉的互连数最少。前一个目的是通过找到最大匹配来实现的,而后者是通过晶体管对的迭代互换来实现的。引入了一种基于信道路由方法的新路由技术来处理内部单元区域。它打算以第一层的主要用途和最少的轨道使用来进行路由。 P>
已开发出一种基于算法的程序,并将其应用于多达200个晶体管的许多模块设计。结果表明,所提出的算法可以实现与手工布局一样好的布局。 P>
机译:GM-Learn:用于CMOS门矩阵布局的迭代学习算法
机译:非常深的亚微米自检电路的组合功能块的信号编码和CMOS门
机译:超深亚微米自检电路组合功能模块的信号编码和CMOS门
机译:CMOS门阵列功能块的自动布局算法
机译:晶体管放置算法,用于CMOS / BiCMOS逻辑和接口电路的自动布局合成。
机译:太赫兹实时成像系统的1×200 CMOS检测器阵列的信号调节模块
机译:CMOS门阵列的自动硬件编译器
机译:CmOs功能阵列的最佳布局。