Weighted-to-residue and residue-to-weighted converters with three-moduli (2/sup n/ - 1, 2/sup n/, 2/sup n/+1) signed-digit architectures

摘要

In this paper, high-speed signed-digit (SD) architectures for weighted-to-residue (WTOR) and residue-to-weighted (RTOW) conversion with the moduli set (2/sup n/ - 1, 2/sup n/, 2/sup n/+1) are proposed. The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse and the properties of modular arithmetic. The simple relationships of WTOR and RTOW result in simpler hardware requirements for the converters. The primary advantages of our method is that our conversions utilize the modulo m signed-digit adder (MSDA) only and the constructions are simple. We also investigate the modular arithmetic between binary and SD number representation by circuit design and simulation, and the results show the importance of SD architectures for WTOR and RTOW.