Frequency characteristic analysis and design of high speed current-steering CMOS digital-to-analog converter

摘要

Based on the analysis for mismatch error and output impedance of high speed digital-to-analog converter, the high level SFDR model of DAC is implemented with mismatch error and output impedance by Matlab. A novel current source circuit is presented in this paper. A 14-bit, 100MS/s DAC is implemented in TSMC 0.35/spl mu/m CMOS technology. The DAC can deliver up to 20mA full-scale current into a 50/spl Omega/ load and occupies 3.8mm/sup 2/ die area. Spurious-free dynamic range (SFDR) is 71dB at a 100MHz clock rate and a 20MHz output frequency.