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Efficacy of the Thermalized Effective Potential Approach for Modeling Nano-Devices

机译:热电势方法对纳米器件建模的功效

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The efficacy of the thermalized parameter-free effective potential approach described elsewhere is examined with regard to its application to modeling of alternative device technologies. Our investigations suggest that the Hartree correction is significant only for very high doping densities, as it is the case in deca-nano MOSFETs. For low doping densities, as it is usually the case in alternative device structures, such as dual-gate and FinFET devices, the Hartree term can be neglected and the Barrier term needs to be included in the model only. Since the Barrier field is pre-calculated in the initialization stages of device simulation, it does not add any additional computational cost, thus leading to a very effective way of including quantum mechanical space-quantization effects in the computational model.
机译:关于在其他器件技术建模中的应用,研究了其他地方所述的无参数热化有效势方法的有效性。我们的研究表明,就像在十纳米MOSFET中一样,Hartree校正仅对于非常高的掺杂密度才有意义。对于低掺杂密度,通常在其他器件结构(例如双栅极和FinFET器件)中通常会出现这种情况,可以忽略Hartree项,而将Barrier项仅包含在模型中。由于势垒场是在设备仿真的初始化阶段预先计算的,因此它不会增加任何额外的计算成本,从而导致一种非常有效的方式将量子力学空间量化效应包括在计算模型中。

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