adders; threshold logic; high-speed techniques; CMOS logic circuits; logic design; low threshold voltage adder; high-speed conditional carry adder; complementary pass-transistor logic; low-voltage application; high-speed application; conditional sum addition rule; adder design; low threshold voltage design; low-voltage arithmetic systems; high-speed arithmetic systems; normal threshold voltage schemes; zero threshold voltage schemes; power-delay product; energy-delay product; power consumption; CPL; VLSI; 62 bit;
机译:高速条件进位选择(CCS)加法器电路,具有递增的进位数字块(SICNB)结构,可实现低压VLSI
机译:高速条件进位选择(CCS)加法器电路,具有连续递增的进位数字块(SICNB)结构,用于低压VLSI实现
机译:具有双阈值电压的高速,低功耗,8位进位前置放大器
机译:64位低阈值电压高速条件通过互补通晶体管逻辑携带加法器
机译:高速条件进位选择加法器的仿真与分析。
机译:两个新颖的低功耗高速动态碳纳米管全加电池
机译:使用能量节电通晶体管逻辑(EEPL)设计低功率108位条件总和加法器