Hardware realization of building blocks for artificial neural networks

摘要

Circuits and layouts of a synapse and a neuron are proposed. The synapse is an improved version of the Gilbert multiplier. The neuron generates both the sigmoid function and its derivative. HSPICE Simulations are carried out using Level 28 transistor models for a 0.5-/spl mu/m CMOS, double-poly, double-metal technology. These building blocks are applied to an on-chip learning neural network. The prototype chip is now under fabrication.