VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter

摘要

We present an implementation of a reconfigurable 16-tap finite impulse response filter for post-processing applications. This filter exploits the distributed arithmetic technique for signal processing and floating-gate voltage references for setting tunable analog coefficients. The filter is fabricated in 0.5mum CMOS process, and its order can be increased at the cost of 0.011mm² of die area and 0.02mW of power per tap. Measurement results for low-pass and band-pass filters at 50kHz sampling frequency are presented.