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VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter

机译：可重构混合信号有限脉冲响应滤波器的VLsI实现

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作者
Walter Huang; Paul Hasler; David V. Anderson;
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年度 2014
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1. A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering [J] . Ozalevli E., Huang W., Hasler P.E., IEEE transactions on circuits and systems . I , Regular papers . 2008,第2期

机译：用于有限冲激响应滤波的分布式算法的可重构混合信号VLSI实现
2. Analysis and Implementation of High Performance Reconfigurable Finite Impulse Response Filter Using Distributed Arithmetic [J] . E. Chitra, T. Vigneswaran, S. Malarvizhi Wireless personal communications: An Internaional Journal . 2018,第4期

机译：分布式算术的高性能可重构有限脉冲响应滤波器的分析与实现
3. Design and implementation of a reconfigurable finite impulse response filter for adaptive systems [J] . R. Saranya, C. Pradeep, R. Radhakrishnan International journal of computational systems engineering . 2017,第1a2期

机译：用于自适应系统的可重构有限冲激响应滤波器的设计与实现
4. VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter [C] . Ozalevli, E., Huang, . 2007

机译：可重构混合信号有限冲激响应滤波器的VLSI实现
5. An efficient architecture for adaptive finite impulse response filters on field programmable gate arrays. [D] . Nallani Chakravartula, Krishna Chaitanya. 2016

机译：现场可编程门阵列上自适应有限冲激响应滤波器的高效架构。
6. Uniform patterns based area-efficient and accurate stochastic computing finite impulse response filter [O] . Muhammad Ijaz, Syed Azhar Ali Zaidi, Aamir Rashid 2021

机译：基于均匀的图案的区域高效和准确的随机计算有限脉冲响应滤波器
7. An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters [O] . Visvanathan V, Mohanty Nibedita, Ramanathan S 1993

机译：实时VLSI有限冲激响应滤波器的高效区域收缩结构

VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter

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