Analog four-quadrant multipliers suffer from errors in the output owing to various factors including process, temperature and bias conditions. In most cases, little can be done to avoid these errors. This paper introduces a new analog four quadrant multiplier that employs the weighted summing capability of the Floating Gate MOSFET (FGMOS). The circuit features a wide input range that exceeds the power supplies (about 240% of the supply), and a novel Electrical Error correction technique. In addition, it has a reasonably high bandwidth (about 32MHz), low Total Harmonic Distortion (THD=0.712%) and high input Dynamic range (130dB).
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