Hot Block Ring Counter: A Low Power Synchronous Ring Counter

摘要

In this paper, we propose a new and low-power architecture for synchronous ring counters which can noticeably reduce the switching activity of the conventional ring counters. To achieve the goal we partition the ring counter into some blocks for each of which we use a special clock gator. The Hot block (the block in which the `1'' exists) is the only block the flip-flops of which are clocked. The delay and area overhead of the proposed clock gator is independent of the block size; this enables designer to freely resize the blocks and compromise with area and power overheads. The latency increase in the proposed architecture is independent of the counter width and depends only on the technology. For 90 nm technology it increases the latency by5%. The architecture noticeably (about 85%) reduces the total switching activity of the counter especially for wide counters.