What if merging connection and switch boxes - an experimental revisit on FPGA architectures

摘要

We propose a new FPGA architecture using the connection-switch box (CS-box). It is based on the symmetric-array FPGA architecture and combines the connection box and the switch box. Two algorithms are designed to build the switches inside CS-boxes, one for logic pins and the other for pad pins. After a theoretical analysis and comparison, we conducted extensive experiments on MCNC benchmark circuits and made comparison between symmetric-array FPGAs and the proposed FPGA architecture on channel widths, circuit delays and switch numbers. By using the CS-box structure, the switch number of the connection boxes can be reduced by up to 11.81% with small penalty of increasing the channel width and the circuit delay by 0.38% and 2.34% on average respectively.