Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins

摘要

To solve the problem of fluctuations in clock timing with digital LSI (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robust clock timing to cope with fluctuations in the LSI environment such as temperature or power supply voltage. This method is realized by the combination of dedicated adjustable circuitry and adjustment GA software, with the values for multiple adjustable delay circuits inserted into the clock lines being determined by the GA software after fabrication. Simulation results show that proposed method can enhance the operational yields of developed test chips by 97% (maximum) while ensuring sufficient timing margins.