A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback

摘要

This paper presents a previously unpublished technique for the reduction of the sensitivity to clock jitter in continuous-time sigma-delta modulators. Therefore, the main clock jitter source, the feedback digital-to-analog converter, is implemented by using a sloping feedback pulse-form, which is generated by a transistor current source and a circuit to generate the slope. In this first implementation, a third-order continuous-time modulator has been designed, achieving 10 bits of resolution and consuming only 250/spl mu/W from a 1.5V supply, while the jitter sensitivity could be remarkably reduced.