A novel multiplier recoding technique and its application to the development of a high-speed parallel online multiply-accumulate architecture

摘要

This paper is concerned with the development of a novel 6-digit overlapped scanning technique for the efficient recoding of signed-binary (SB) numbers in their minimally redundant base-4 representation having (-2, -1, 0, 1, 2) as their digit set. This technique permits a reduction of the number of partial products in a multiplication by a factor of two if applied to multiplier recoding (in much the same manner as the modified-Booth recoding technique), with the added advantage of being applicable to purely SB multiplication. The proposed 6-digit overlapped scanning technique is applied to the development and the subsequent FPGA hardware is translated into an architecture for parallel online purely SB MAC operation.