首页>
外国专利>
MULTIPLIER-ACCUMULATOR CIRCUIT, LOGIC TILE ARCHITECTURE FOR MULTIPLY-ACCUMULATE AND IC INCLUDING LOGIC TILE ARRAY
MULTIPLIER-ACCUMULATOR CIRCUIT, LOGIC TILE ARCHITECTURE FOR MULTIPLY-ACCUMULATE AND IC INCLUDING LOGIC TILE ARRAY
展开▼
机译:乘法器蓄电池电路,用于乘法累积和IC的逻辑瓦片架构,包括逻辑块阵列
展开▼
页面导航
摘要
著录项
相似文献
摘要
An integrated circuit comprising a plurality of multiply-accumulator circuits, connected in series, wherein the plurality of multiply-accumulator circuits includes a first MAC circuit, including a multiplier to multiply first data and first multiplier weight data and output first product data, and an accumulator, coupled to the multiplier of the first MAC circuit, to add second data and the first product data and output first sum data. The plurality of multiply-accumulator circuits further includes a second MAC circuit including a multiplier to multiply third data and second multiplier weight data and output second product data, and an accumulator, coupled to the multiplier of the second MAC circuit and the accumulator of the first MAC circuit, to generate and output second sum data. A first load-store register is coupled to an output of the accumulator of the first MAC circuit and an input of the accumulator of the second MAC circuit.
展开▼