A digital Class D amplifier design embodying a novel sampling process and pulse generator

摘要

A digital Class D amplifier comprises a digital Pulse Width Modulation (PWM) and an output stage (and low pass filter). Digital PWM involves two steps, the sampling process and the pulse generation. In this paper, we propose a digital Class D amplifier based on our sampling process and a novel PWM pulse generator design. The pulse generator is based on the combination of the fast clock counter and the tapped delay line based techniques. Our proposed Class D amplifier features a simple circuit implementation (small IC area), low power operation (expected /spl sim/90 /spl mu/W@1.1 V, f/sub sampling/=16 kHz based on a 0.25 /spl mu/m CMOS process) and a highly desirable low harmonic distortion (expected >0.7%).