FPGA implementation of a DSP core for full rate and half rate GSM vocoders

摘要

Global System for Mobile (GSM) communications uses a 13 kbps vocoder which expands to 22.8 kbps after channel coding. To increase the user capacity, the half rate channel has a gross transfer rate 11.4 kbps. The vocoder for the half rate channels operates at 5.6 kbps. The computational requirements of these vocoders and other necessary services require the design of an entirely new digital signal processing architecture geared towards 1D signal and speech processing. The suggested architecture is characterized by pipelining and parallel operation of functional units. This core is a 16-bit fixed point processor implemented on FPGA, and can be used as a real time GSM speech vocoder.