Phase-jitter dynamics in second-order DPLLs with irrational and integer input frequencies

摘要

As a result of frequency quantization in a digital phase-locked loop (DPLL), the device cannot in general track the input signal exactly but instead exhibits in its limit behaviour small unwanted oscillations called "phase jitter". In recent studies we investigated this phase jitter in a second-order DPLL with sinusoidal input from the viewpoint of the theory of nonlinear dynamics, paying attention mainly to the case of non-integer rational input frequency and small values of gains in the loop. In this paper we shall extend that work to encompass the cases of irrational and integer input signals, and increased gains.