A 1-GHz phase-locked loop (PLL) is implemented in 0.5-/spl mu/m CMOS to generate a 500-MHz clock with 50% duty. The voltage-controlled oscillator (VCO) combined with the differential charge pump is employed to have low clock skew and better immunity to the noises from supply, ground and substrate. The long-term peak-to-peak jitter of less than 70 psec and 165 psec are achieved for the quiet supply line and for the noisy one modulated by 400-mV/sub p-p/, 500-kHz square wave, respectively. The prototype 1-GHz PLL consumes 55 mW with 3.3-V supply. The PLL with the phase interpolation technique is also investigated and its performance is compared to the standard approach.
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机译：在0.5- / spl mu / m CMOS中实现了1 GHz锁相环（PLL），以生成占空比为50％的500 MHz时钟。压控振荡器（VCO）与差分电荷泵结合使用，具有较低的时钟偏斜并且对来自电源，地和基板的噪声具有更好的抗扰性。对于安静的电源线和通过400mV / sub p-p /，500kHz方波调制的有噪声的电源线，分别实现了小于70ps和165ps的长期峰峰值抖动。原型1 GHz PLL在3.3 V电源下的功耗为55 mW。还研究了采用相位插值技术的PLL，并将其性能与标准方法进行了比较。
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