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Design and implementation for 125 mW/MIPS ultra-high speed low power asymmetric digital subscriber line transceiver chip

机译:125 mW / MIPS超高速低功耗非对称数字用户线收发器芯片的设计与实现

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Multimedia service with audio and video have become most desirable as the ADSL technology ideally converted from 1.5 Mbps full duplex HDSL technology via two twist-pair into 6.144 Mbps transmission technology via single twist-pair. This results in an interactive transmission service of T1 & E1 class data using the subscriber line without repeaters. The ADSL transceiver chipset is configured by DMT (Discrete Multi Tone modulation) scheme and RISC-based DSP core structure. Our ADSL chip is to be used in VOD, interactive interact service and/or teleconferencing system, etc. The operating frequency and dissipated power of the chip are 40 MHz and 5 W at 5 V.
机译:随着ADSL技术理想地从通过两个双绞线对的1.5 Mbps全双工HDSL技术转换为通过单个双绞线对的6.144 Mbps传输技术,带音频和视频的多媒体服务已成为最理想的选择。这导致使用没有中继器的用户线进行T1和E1类数据的交互式传输服务。 ADSL收发器芯片组通过DMT(离散多音频调制)方案和基于RISC的DSP内核结构进行配置。我们的ADSL芯片将用于VOD,交互式交互服务和/或电话会议系统等。该芯片的工作频率和耗散功率分别为40 MHz和5 V在5V。

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