A high-speed residue-to-binary converter and a scheme for its VLSI implementation

摘要

In this paper, a high-speed residue-to-binary converter for the recently introduced moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40% faster; also, the time-complexity product is improved by 20%. Following the VLSI design flow established by the Canadian Microelectronics Corporation, the proposed converter is implemented in 0.5-micron CMOS technology. Based on this moduli set, layouts of the 8-bit, 16-bit, 32-bit and 64-bit residue-to-binary converters which can be used in further RNS system designs, are generated and simulation results obtained.