This paper presents an efficient architecture for decompressing fractal-based compressed images and its VLSI implementation with high decoding speed and low hardware cost. The chip is fabricated using 5 V, 1 poly 3 metal, 0.6 /spl mu/m CMOS technology. The proposed VLSI architecture uses the Modified Recursive Decoding Algorithm (MRDA), which reduces the number of iterations and hardware areas. The proposed decoder architecture shows that RAM size is reduced by 50% and the decoding speed to get final attractor (reconstructed image) is improved by 50%, compared with conventional method using Classical Recursive Decoding Algorithm(CRDA). Based on the operating frequency(50 MHz), the decoder can produce about 70-80 image frames(256/spl times/256) per second. Therefore, it can decode 2-D quadtree partitioned fractal images in real time.
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机译：本文提出了一种用于解压缩基于分形的压缩图像的高效架构及其VLSI实现，具有很高的解码速度和较低的硬件成本。该芯片是使用5 V，1聚3金属，0.6 / spl mu / m CMOS技术制造的。提出的VLSI体系结构使用了改进的递归解码算法（MRDA），从而减少了迭代次数和硬件区域。与传统的经典递归解码算法（CRDA）相比，所提出的解码器架构显示RAM减小了50％，获得最终吸引子（重构图像）的解码速度提高了50％。根据工作频率（50 MHz），解码器每秒可产生约70-80个图像帧（256 / spl次/ 256）。因此，它可以实时解码二维四叉树分割的分形图像。
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