Fully integrated LVD clock generation/distribution IC

摘要

This paper describes a clock generation and distribution IC, The design contains a fully differential PLL with a 1 GHz VCO and programmable dividers to form a frequency synthesizer with two synchronous output frequencies from 7.7 MHz to 500 MHz. LVD, low voltage differential, output drivers provide 12 low skew copies of the synthesized frequency with on chip termination. The module can be used as either a frequency synthesizer and distributor or as a distributor alone. The design obtains +/-20 ps cycle-cycle jitter, 40 ps driver-driver skew and 180 ps chip to chip skew. The fully integrated design is implemented on a 2.85 mm by 3.3 mm chip in a 3.3 V, 0.45 um L/sub eff/ BiCMOS technology with 12 GHz f/sub t/ npn's and is packaged in a 68 pin PLCC.