This paper presents a new timing-driven global routing method for standard cell layout. The proposed method can explicitly consider the timing constraint between two registers and minimize the channel density under the given timing constraint. First, we determine the initial global routes. Next, we improve the global routes to satisfy the timing constraint between two registers as well as to minimize the channel density. Finally, for each cell row, the nets incident to terminals an the cell row are assigned to channels to minimize the channel density using 0-1 integer linear programming. We also show experimental results of the proposed method implemented on an engineering workstation, which show that the proposed method is quite promising.
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