A minimal source-synchronous interface

摘要

We present a novel implementation of source synchronous communication for communication between clock domains within a SOC. Our design appears to the designer as a latch with two clock inputs, one from the transmitter and the other from the receiver. Our circuit is simple and provides a skew tolerance of nearly two clock periods. The analog dynamics of our circuit provide a simple initialization mechanism that maximizes the robustness of the interface to skew variations.