A high-level data path allocation algorithm based on BIST testability metrics

摘要

In this paper, we describe a BIST testability metric-based high-level data path allocation algorithm to facilitate Built-In Self-Test designs. We will describe register transfer level data path testability metrics to evaluate various BIST configurations and make improvement decision during the data path allocation. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.