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Test Circuit Structures For Characterizing The Effects Of Localized Hot-carrier-induced Charge In VLSI Switching Circuits

机译：测试电路结构，用于表征VLSI开关电路中局部热载流子感应电荷的影响

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《》|2001年|P.126-131|共6页
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Suehle; J.S.; Galloway; K.F.;
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中图分类无线电电子学、电信技术;
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1. Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits [J] . Rau J.C., Jone W.B. IEE proceedings. Part E . 2000,第5期

机译：用于VLSI电路的虚拟穷举测试的树状LFSR综合方案
2. Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits [J] . J.C.Rau, W.B.Jone, S.C.Chang, IEE proceedings. Part E . 2000,第5期

机译：用于VLSI电路的虚拟穷举测试的树状LFSR综合方案
3. A WAVEFORM-BASED GATE-LEVEL TIMING SIMULATOR (BTS) FOR MOS VLSI CIRCUITS WITH THE CONSIDERATIONS OF THE INTERNAL CHARGE EFFECTS [J] . Jims J. H. Wang, Molin Chang, Wu-Shiung Feng Journal of the Chinese Institute of Engineers . 1995,第2期

机译：考虑内部电荷效应的基于波形的门极时序仿真器（BTS），用于MOS VLSI电路
4. Test Circuit Structures For Characterizing The Effects Of Localized Hot-carrier-induced Charge In VLSI Switching Circuits [C] . Suehle J.S., Galloway K.F., Institute of Electric and Electronic Engineer IEEE International Conference on Microelectronic Test Structures . 2001

机译：测试电路结构，用于表征局部热载波诱导电荷在VLSI开关电路中的影响
5. Charge collection studies on integrated circuit test structures using heavy-ion microbeams and MEDICI simulation calculations. [D] . Guo, Baonian. 2000

机译：使用重离子微束和MEDICI模拟计算对集成电路测试结构进行电荷收集研究。
6. Design of synthetic epigenetic circuits featuring memory effects and reversible switching based on DNA methylation [O] . Johannes A. H. Maier, Raphael Möhrle, Albert Jeltsch -1

机译：基于DNA甲基化的具有记忆效应和可逆转换的合成表观遗传电路设计
7. Ion beam induced charge collection (IBICC) from integrated circuit test structures using a 10 MeV carbon microbeam [O] . B. N. Guo, S. N. Renfrow, B. L. Doyle, 1999

机译：离子束诱导电荷收集（IBICC）来自集成电路测试结构的使用10meV碳微磁束
8. Ion Beam Induced Charge Collection (IBICC) from Integrated Circuit Test Structures Using a 10 MeV Carbon Microbeam [R] . Aton, T. J. , Doyle, B. L. , Duggan, J. L. , 1998

机译：使用10 meV碳微束从集成电路测试结构中获得离子束感应电荷（IBICC）

Test Circuit Structures For Characterizing The Effects Of Localized Hot-carrier-induced Charge In VLSI Switching Circuits

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