A 128/spl times/128 CMOS imager with 4/spl times/128 bit-serial column-parallel PE array

摘要

A 4/spl times/128 fine-grained bit-serial processing element array configured with four 1/spl times/128 SIMD processors is embedded in 128/spl times/128 pixel CMOS imager columns. The prototype imager chip performs /spl sim/220 operations/pixel at 20 MHz clock, which potentially affords pixel-rate color processing for a VGA format image.