An interpolating analog-to-digital converter (ADC) using pipelined architecture is designed. In order to obtain a high linearity of the ADC, a differential difference amplifier (DDA) with well restrained nonlinearity error is adopted to reduce the nonlinearity error. Furthermore, a latched comparator is proposed to achieve a low kickback noise, which is of great importance to the linearity of the ADC. The ADC is implemented in a 0.35μm standard digital CMOS process with a single 3.3V supply, and achieves 8bit resolution at speeds up to 50 Msamples/s.
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