Per-bit sense amplifier scheme for 1GHz SRAM macro in sub-100nm CMOS technology

摘要

A sensing circuit is developed in order to produce a 1 GHz SRAM macro to be used in sub-100 nm CMOS technology nodes. It employs a sense amplifier for each bit-line pair in high-speed operations. The amplifier's optimized composition consists of just ten transistors and helps to minimize area overhead.