We have developed and demonstrated a 3D multi-scale thermal-analysis methodology for multiple and stacked-chip configurations. This approach employs a global-local problem-domain discretization in conjunction with the floating RW (random walk) method. Emphasis has been placed on capturing complex thermal effects due to interconnect layers. We have analyzed a hypothetical stacked-chip geometry derived from a Stanford interconnect test chip. 2D gdsII layout data was automatically processed and converted into a 3D problem domain. On a 400 MHz Apple PowerBook G3/sup TM/, execution time was about three minutes per temperature data point. Temperature at each evaluated point was computed with 1000 RWs, yielding a 1-/spl sigma/ statistical error of about 5%. Based on heuristic formulas that we have deduced, a local window of /spl plusmn/20 /spl mu/m relative to the RW start point achieved a reasonable global-local discretization error.
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