首页> 外文会议> >A built-in self-reconfigurable scheme for 3D mesh arrays
【24h】

A built-in self-reconfigurable scheme for 3D mesh arrays

机译:用于3D网格阵列的内置自可重新配置方案

获取原文

摘要

We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line from a faulty processor to a spare on the surfaces. Two opposite directions are allowed for compensation paths only which they are not in the near-miss relation. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults and show the survival rates and the probabilities of them by computer simulation. The probabilities are compared with those of the case using double tracks which have no restriction of the near-miss relation. The algorithm can reconfigure the 3D mesh arrays in polynomial time. Finally, we design a logical circuit for hardware realization of the algorithm. This will be able to make us build such a built-in self-reconfigurable 3D mesh array that the reconfiguration can be done very quickly.
机译:我们提出了一种使用半跟踪开关的容错3D处理器阵列模型。备用处理器放置在3D阵列的两个相对表面上。通过将处理器以连续的直线从故障处理器移动到表面上的备用处理器来执行故障补偿过程。补偿路径只允许两个相反的方向,它们不处于接近未命中的关系。然后,仅需4种状态的开关即可在补偿故障后保留3D网格拓扑。我们以一种方便的形式给出了一种算法,用于通过硬件重新配置有故障的3D网格阵列,并通过计算机仿真显示其存活率和概率。将这些概率与使用双轨的情况进行比较,该双轨没有对未遂关系的限制。该算法可以在多项式时间内重新配置3D网格阵列。最后,我们设计了用于该算法的硬件实现的逻辑电路。这将使我们能够构建这样一个内置的可自我重新配置的3D网格阵列,从而可以非常快速地完成重新配置。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号