A novel architecture and processor-level design based on a new matching criterion for video compression

摘要

In this paper, architectures which can support the block-based real time motion estimation of video signals using various search methods have been presented. The design efforts are focused on the processor-level design with a new matching criterion. With the new binary level matching criterion which performs a bit-wise comparison instead of the conventional eight-bit addition/subtraction, we could achieve a simple processor-level design with fewer input/output lines and lower power consumption.