VHDL 1076.1-analog and mixed-signal extensions to VHDL

摘要

This presentation provides an overview of the 1076.1 effort to extend the well established VHDL language to support the description and simulation of continuous and mixed continuous/discrete systems. It begins with a brief history of the effort. That is followed by an overview of the foundations: the design objectives, the base VHDL 1076 language, and the applicable mathematical theory. The body of the presentation describes the elements of the extended language. Each language element is described in the context of the 1076.1 language architecture and illustrated by a brief example. The presentation ends with selected examples illustrating the use of the language for analog and mixed-signal applications.