An integrated approach to pin assignment and global routing for VLSI building-block layout

摘要

An efficient algorithm integrating global routing, pin assignment, block reshaping and positioning, which is based on a rip-up and reroute and the simulated evolution technique, is presented. Experimental results show that the proposed algorithm achieves up to 10.5% reduction of chip area and up to 34.6% reduction of total wire length compared with previous methods.