Generalized delay optimization of resistive interconnections through an extension of logical effort

摘要

The resistance of VLSI interconnections is significant. Previous studies have proposed optimal repeater schemes using simple buffers for delay optimization of the interconnection. A more general approach that handles arbitrary logic gates as well as buffers is proposed. The methodology is based on an extension of the concept of logical effort. The optimization yields proper spacing of the given logic gates, additional repeaters (buffers) required for a given RC line, and sizing of all the gates. This approach is applicable to design situations where existing CMOS logic gates must be considered in the overall repeater scheme.