SHILPA: a high-level synthesis system for self-timed circuits

摘要

SHILPA is a system for the high-level synthesis of self-timed circuits. It takes behavioral descriptions in a process+functional language called hopCP and produces a netlist for the Actel field-programmable gate array (FPGA), supported by the VIEWlogic tools. hopCP descriptions are initially translated into an intermediate form based on hypergraphs called HFGs. SHILPA then applies action refinement, which is a technique for transforming HFGs into asynchronous hardware by a series of graph-based transformation rules. Action refinement is characterized by incremental resource allocation and control decomposition. The major contributions of the proposed work are given.