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SHILPA: A High-Level Synthesis System for Self-Timed Circuits

机译：SHILPA：用于自定时电路的高级综合系统

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Venkatesh Akella;
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年度 1992
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1. Preventing Glitches and Short Circuits in High-Level Self-Timed Chip Specifications [J] . Longfield Stephen, Nkounkou Brittany, Manohar Rajit, ACM SIGPLAN Notices: A Monthly Publication of the Special Interest Group on Programming Languages . 2015,第6期

机译：防止高级自定时芯片规格出现毛刺和短路
2. A method for the automatic translation of algorithms from a high-level language into self-timed integrated circuits [J] . Kelem Steven H. Circuits and Devices Magazine, IEEE . 1985,第2期

机译：一种将算法从高级语言自动转换为自定时集成电路的方法
3. On Self-Timed Circuits in Real-Time Systems [J] . Markus Ferringer International journal of reconfigurable computing . 2011,第3期

机译：实时系统中的自定时电路
4. SHILPA: a high-level synthesis system for self-timed circuits [C] . Akella, V., Gopalakrishnan, . 1992

机译：SHILPA：用于自定时电路的高级综合系统
5. Algorithms for coupling circuit and physical synthesis with high-level design-space exploration for 2D and 3D systems. [D] . Mukherjee, Madhubanti. 2004

机译：用于2D和3D系统的电路和物理综合与高级设计空间探索的耦合算法。
6. Synthesis of Arbitrary Quantum Circuits to Topological Assembly: Systematic Online and Compact [O] . Alexandru Paler, Austin G. Fowler, Robert Wille -1

机译：任意量子电路到拓扑组装的综合：系统在线和紧凑
7. IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [O] . Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha 1998

机译：影响：低功耗控制流强化电路的高级综合系统
8. Method for the Automatic Translation of Algorithms from a High-Level Language into Self-Timed Integrated Circuits [R] . Kelem, S. H. 1986

机译：从高级语言到自定时集成电路的算法自动转换方法

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