IEE Colloquium on 'Processing Issues for VLSI/ASIC Designers' (Digest No.152)

摘要

The following topics were dealt with: packages for gate arrays and standard cells; mixed analogue-digital ASIC processing issues; SOI for high-performance ASIC designs; fabrication technology for ASIC and VLSI designers; and scalable design rules vs. rule based compilation/compaction.